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GT-48006A low cost two port 10/100 ethernet bridge/switch controller preliminary revision 1.2 8/4/98 please contact galileo technology for possible updates before finalizing a design. features www.galileot.com support@galileot.com tel: +1-408.367.1400 fax: +1-408.367.1401 ? single-chip, low-cost, two port 10/100mbps ethernet bridge/switch - provides packet switching functions between two 10/100mbps, auto-negotiated on-chip fast ethernet ports - ideal for dual speed repeater and 2-port bridge applications ? incorporates two 802.3 compliant 10/100mbps media access controllers - direct interface to mii (media independent interface) - half/full duplex support (up to 200 mbps/port) - ieee 802.3 100base-tx, t4, and fx compatible - support for backpressure in half-duplex mode ? auto-negotiation supported through mii interface - can be disabled on a per-port basis ? high-performance switching engine - performs forwarding and filtering at full wire speed - 148,800 packets/sec on each ethernet port ? direct support for packet buffering - glueless interface to 1or 2mbyte of 50ns edo dram - up to 1k buffers, 1536-bytes each - dynamic or fixed buffer allocation for each port ? supports store and forward switching approach - low last-bit in to first-bit out delay - provides packet buffering in overloaded networks ? high visibility led interface - 3 pin serial led interface for detailed status information per port ? advanced address recognition - intelligent address recognition mechanism enables forwarding rate at full wire speed - self-learning mechanism - supports up to 16k unicast addresses and unlimited multicast/broadcast addresses ? low-power 0.5u 3.3v process (5v tolerant) ? 100 pin pqfp package GT-48006A edo dram 10/100 repeater chip four ports 10/100baset 10/100 repeater chip four ports 10/100baset 10/100 repeater chip four ports 10/100baset 10/100 repeater chip four ports 10/100baset 100 mbps segment 10 mbps segment
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 2 1. functional overview the GT-48006A is a high-performance/low-cost, two-port 10/100mbps ethernet bridge/switch that provides packet switching/bridging functions between two on-chip 10/100mbps auto-negotiated ports. the GT-48006A is intended for applications that need to bridge between two 10/100basex collision domains, such as: ? autonegotiating dual speed 10/100 repeaters ? unmanaged 10/100 bridges ? fiber to 100basetx media converters the GT-48006A provides no network management functions (other than leds). oems requiring management should consider the gt-48002a and gt-48004a 100basetx switches, or galileos galaxy tm family of low-cost desktop switching components (the gt-48212 and gt-48208.) 1.1 fast ethernet ports the GT-48006A integrates two fast ethernet ports each capable of operation at 10/100mbps (half-duplex) or 20/ 200mbps (full-duplex). two media independent interfaces (mii) are provided for glueless connection to off-the-shelf phy chips. the GT-48006A supports full auto-negotiation for capable phys. the speed (10 or 100 mbps) and duplex (half or full) to which the phy resolves to operate is automatically reported to the GT-48006A. the port can also be forced to operate in a specific duplex mode, if so desired. each port includes the media access control function (mac); the serial led and mdc/mdio interface is shared between the ports. the fast ethernet ports support backpressure in half-duplex mode. when backpressure is enabled, and there is no receive buffer available for incoming traffic, the GT-48006A will force a jam pattern on the receiving port. 1.2 address recognition the GT-48006A can recognize up to 16,000 different unicast mac addresses and unlimited multicast/broadcast mac addresses. an intelligent address recognition mechanism enables filtering and forwarding packets at full fast ethernet wire speed. 1.3 dram interface GT-48006A interfaces directly to 1mbyte or 2mbyte of edo dram. the dram is used to store the incoming/outgoing packets as well as the address table and other device data structures. the interface to edo dram is glueless; all sig- nals needed to control edo devices are provided. 1.4 packet buffers incoming packets are buffered in the dram array. these buffers provide elastic storage for transferring data between low-speed and high-speed segments. the packet buffers are managed automatically by the GT-48006A.
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 3 2. pin information 2.1 logic symbol rst* clk ddata[31:0] ras[1:0]* cas* we* gt-48006 daddr[8:0] dram mii interface 9 leddata ledstb ledclk miscellaneous interface 32 scan* tristate* txclk[1:0] txd0[3:0 ] col[1:0] rxd0[3:0] rxer[1:0] 2 2 4 2 4 2 rxclk[1:0] rxdv[1:0] crs[1:0] 2 2 2 txd1[3:0] 4 rxd1[3:0] 4 mdc mdio txen[1:0] interface vtol 2 aging
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 4 3. pin functions and assignment symbol type description clock and reset rst* i reset: active low. rst* must be asserted for at least 10 clock cycles when in the reset state. following rst* deassertion, the GT-48006A clears the inter- nal buffers and initializes the address table in the dram. the address table initialization takes 165,000 clk cycles to complete. any incoming packets dur- ing address table initialization are ignored. clk i clock: provides the timing for the GT-48006A internal units. all functional units except for the serial interfaces use this clock.the clock frequency is 40mhz. this input is not 5v tolerant. dram interface ddata[31:0] i/o dram data: 32-bit edo dram data bus. these signals connect directly to the data input/output pins of the dram devices. daddr[8:0] i/o dram multiplexed address bus: in normal operation, daddr[8:0] contain the dram multiplexed row/column address. during reset, these multiplexed pins are sampled by the GT-48006A to indicate various parameters as follows: daddr[0] - autonegotiation enable for port 0 daddr[1] - autonegotiation enable for port 1 daddr[2] - skip init daddr[3] - limit4 daddr[4] - vl tag enable passing daddr[5] - dram size daddr[6] - full duplex for port 0 daddr[7] - full duplex for port 0 daddr[8] - back pressure enable ras[1:0]* o row address strobes: dram row address strobes. for the two banks. cas* o column address strobe: dram column address strobe. the GT-48006A always accesses 32-bit values and does not require a separate cas* for each byte. we* o write enable: dram write enable. media independent interface txen[1:0] o transmit enable: active high. this output indicates that the packet is being transmitted. txen is synchronous to txclk. txclk[1:0] i transmit clock: provides the timing reference for the transfer of txen, txd signals. txclk frequency is one fourth of the data rate (25 mhz for 100mbps, 2.5 mhz for 10mbps). txclk nominal frequency should match the nominal fre- quency of rxclk for the same port. txd0[3:0] o transmit data 0: outputs the port0 transmit data. synchronous to txclk[0]. txd1[3:0] o transmit data 1: outputs the port1 transmit data. synchronous to txclk[1]. col[1:0] i collision detect: active high. indicates a collision has been detected on the wire. this input is ignored in full-duplex mode. col is not synchronous to any clock. rxd0[3:0] i receive data 0: port 0 receive data. synchronous to rxclk[0]. rxd1[3:0] i receive data 1: port 1 receive data. synchronous to rxclk[1].
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 5 rxer[1:0] i receive error . active high. indicates that an error was detected in the received frame. this input is ignored when rxdv for the same port is inactive. rxclk[1:0] i receive clock . provides the timing reference for the transfer of the rxdv, rxd, rxer signals (per port). operates at either 25 mhz (100mbps) or 2.5 mhz (10mbps). the nominal frequency of rxclk (per port) should match the nominal frequency of that ports txclk. rxdv[1:0] i receive data valid: active high. indicates that valid data is present on the rxd lines. synchronous to rxclk. crs[1:0] i carrier sense: active high. indicates that either the transmit or receive medium is non-idle. crs is not synchronous to any clock. mdc o management data clock: provides the timing reference for the transfer of the mdio signal. this output may be connected to the phy devices of both ports. mdio i/o management data input/output: this bidirectional line is used to transfer control information and status between the phy and the GT-48006A. it con- forms with ieee std 802.3u. this signal may be connected to the phy devices of both ports. when not in use this pin must be connected to a pull-down resis- tor. miscellaneous interface pins leddata i/o led data/disbufthr: in normal configuration carries the serial data bit stream which contains the led indicators per port. the data is shifted out using the ledclk. ledstb is used to mark the first data bit. this pin is active low. during reset, this pin is sampled by the GT-48006A for dynamic/fixed buffering alloca- tion. ledstb i/o led strobe/force link pass: in normal operation indicates the beginning (data bit #1) of a valid data frame on leddata output - active high. during reset, this pin is sampled by the GT-48006A to force the link to pass. ledclk o led clock: 1 mhz clock. this output is used to clock the ledstb and led- data outputs. during reset, ledclk frequency is 40 mhz. scan* i scan: this pin together with tristate* indicate the GT-48006A mode of opera- tion as follows: factory test modes are reserved and are not to be used in-system. failure to observe this restriction could result in damage to the device. tristate* i tri state: this pin together with scan* indicate the GT-48006A mode of oper- ation as described above. symbol type description scan* tristate* mode 1 1 normal operation 0 1 factory test mode (reserved) 1 0 the GT-48006A drives all out- puts and i/o pins to high imped- ance. 0 0 factory test mode (reserved)
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 6 vtol i input voltage tolerance: these pins are connected to the 5v supply to sup- port 5v tolerance on GT-48006A i/os. for pure 3.3v operation connect these pins to the 3.3v supply. aging i aging control: active low. this pin enables/disables automatic address aging within the GT-48006A. symbol type description
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 7 4. reset configuration the GT-48006A uses several pins as configuration inputs to set certain parameters following a reset. the definition of the configuration pins changes immediately after reset to their usual function. 4.1 configuration pins configuration pins must be pulled up or down externally at reset to select the desired operational parameter. the recommended value of the pull-up/down resistors is 4.7k ohms. table 1 on page 7 shows the configuration pins for gt- 48006a. 1. this setting was listed incorrectly in previous revisions of this document. please check your design and ensure that you have the proper pin strapping option for auto negotiation. table 1: reset pin strapping options pin configuration function daddr[1:0] 0- 1- auto negotiation enable for port 1 and 0 1 enable disable daddr[2] skip init 0- 1- skip initialization on reset dont skip initialization daddr[3] limit4 0- 1- disable (standard backoff) enable daddr[4] vl tag enable 0- 1- enable - pass up to 1522 bytes packets disable - pass up to 1518 bytes packets daddr[5] dram size 0- 1- 2mbyte 1mbyte daddr[6] half/full duplex mode for port 0 0- 1- half duplex full duplex daddr[7] half/full duplex mode for port 1 0- 1- half duplex full duplex daddr[8] backpressure 0- 1- disable enable ledstb force link pass 0- 1- force link status to link is up read link status from the phy via smi leddata disable buffer threshold 0- 1- fixed buffer allocation dynamic buffer allocation
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 8 4.2 configuration input timings the configuration inputs have two timing requirements: ? setup/hold time to clock (as any synchronous input) ? setup of at least 10 clock cycles before reset de-assertion (rising edge). these parameters are set by using resistors to strap the configuration pins and delaying reset de-assertion until least 10 clock cycles after the clock is stable.
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 9 5. operational overview the GT-48006A uses a store-and-forward switching approach. store-and-forward was chosen for the following rea- sons: ? store-and-forward switches allow switching between differing speed media (e.g. 10basex and 100basex.) such switches require the large elastic buffers that are provided by the edo dram arrays. this is especially true when bridging between a server on a 100mbps network and clients on a 10mbps segment. ? store-and-forward switches improve overall network performance by acting as a network cache, effectively buffering packets during times of heavy congestion. ? store-and-forward switches prevent the forwarding of corrupted packets by analyzing the frame check sequence (fcs) before forwarding to the destination port. 5.1 basic operation the basic operation of the GT-48006A is quite simple. the GT-48006A receives incoming packets from one of its ports, searches in the address table for the destination mac address and then forwards the packet to the other port, if appropriate. if the destination address and source address are not found in the other ports address table, the GT-48006A treats the packet as a multicast packet and forwards the packet to the other port. the GT-48006A automatically learns the port number of attached network devices by examining the source mac address of all incoming packets. if the source address is not found in the GT-48006As address table, the device adds it to the table. 5.2 address learning the GT-48006A can learn up to 8k unique mac addresses. addresses are stored in the address table located in dram. the address table is managed automatically by the GT-48006A (i.e. new addresses are automatically added to the address table). the GT-48006As address learning process is outlined in section 6. 5.3 packet buffering the GT-48006A supports up to 1008 full packet size receive buffers. these buffers can be dynamically allocated to the two receive ports or can be optionally limited on a per port basis. when working in dynamic buffer allocation mode, the GT-48006A supports 1008 buffers in 2mbyte dram configuration and 308 buffers in 1mbyte dram configuration. in fixed buffer mode, the GT-48006A supports 140 buffers per port in 1mbyte dram, and 320 buffers per port in the 2mbyte configuration. buffer allocation mode is selected via a reset strapping option as shown in table 1 on page 7. 5.4 packet forwarding once an address has been learned, and the packet is buffered, it must be forwarded. the packet forwarding mecha- nism for the GT-48006A is handled automatically based on the destination address. 5.5 terminology it is important to understand the basic terminology used to describe the GT-48006A before getting into a detailed description. table 2 on page 9 explains the terms used throughout this document. table 2: terminology term definition address table the address table is a data structure in the GT-48006As dram that con- tains all learned mac addresses, and routing information associated with those addresses. source address the source address (sa) is the mac address from which a received packet was sent.
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 10 destination address the destination address (da) is the mac address to which a received packet was sent. port number each ethernet port on the gt-48006 has an associated port number. the GT-48006A associates port numbers with the mac addresses located on those ports. table 2: terminology term definition
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 11 6. mac address learning process the GT-48006A has a self-learning mechanism for learning the mac addresses of attached ethernet devices in real time. the GT-48006A searches for the source address (sa) of an incoming packet in the address table and acts as follows: if the sa was not found in the address table (a new address), the GT-48006A waits until the end of the packet (non errored packet) and updates the address table. 6.1 address recognition the GT-48006A forwards the incoming packets between bridge ports according to destination address (da) as fol- lows: 1. if the da is a unicast address and the address was found in the address table, the GT-48006A acts as follows: ? if the port number is equal to the port on which the packet was received, the packet is discarded. ? if the port number is different, the packet is forwarded across the bridge. 2. if the da is a unicast address and the address was not found (unknown), the GT-48006A acts as if it the unknown packet is a multicast packet and forwards across the bridge. 3. if the da is a multicast address, the packet is forwarded across the bridge. 6.2 address recognition failure it is possible that an address recognition cycle will fail when more than 8k addresses have already been entered into the address table. in the case of an address recognition failure the packet will be treated as unknown and forwarded to all ports. address recognition failures are not fatal and do not need to be handled (i.e. designers need not worry about them.) 6.3 address aging address aging is supported for topology changes such as an address moving from one port to the other. when this happens, the GT-48006A detects the change and updates its address table accordingly. addresses of stations perma- nently removed from the network are not aged or removed from the address table. if you wish to age out (remove) these addresses, reset the GT-48006A. there will be a short interruption of traffic flow, however, this is taken care of by the higher-layer protocols. pin 25 is designated to enable or disable the function. in revision prior to the gt48006a, pin 25 is used as a vtol input, and must be tied high . in the current part, GT-48006A, tying pin 25 high will disable address aging. therefore, designs which use versions prior to the GT-48006A must have a stuffing option to tie this pin to ground in order to enable address aging with the gt48006a. see pin descriptions for more information. future revisions of the gt- 48006 will be completely backwards compatible with the current revisions the aging interval will be fixed at 250 seconds based on a 40mhz clock input, or 300 seconds based on a 33mhz clock input to the GT-48006A. addresses which have not been seen within the timer period will automatically be removed from the address table.
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 12 7. GT-48006A buffers and queues the GT-48006A incorporates two transmit queues for the 2 ethernet ports and one common receive buffer area (see figure 1.) the receive buffers as well as the transmit queues are located in the dram along with the address table. the GT-48006A data structure components are the following: ? receive buffer - a common receive buffer area for all ports. the buffer is divided into 308 or 1008 blocks (depending on the dram size) of 1.5kbytes (1536 bytes) each. each block contains an entire packet. ? rx empty list - a list of 308 or 1008 bits. each bit contains the status of its appropriate receive block in the dram (empty or occupied). ? tx descriptors - a set of 2 transmit descriptor rings. each ring contains 1024 descriptors. the descriptor size is one 32-bit word and contains the block address divided by 0x600 (1.5k), the byte count and the packet type (multicast or unicast). ? read/write pointers - 2 pairs of pointers to the transmit descriptors. figure 1: GT-48006A buffers and queues 7.1 rx buffer options there are two modes of operation for the rx buffers: dynamic buffer allocation and fixed buffer size. buffer allocation mode is selected via a reset strapping option as shown in table 1 on page 7. in dynamic buffer allocation mode, each port uses receive buffers from a common pool of available buffers. there are 1008 buffers available with 2 mbyte of dram, 308 buffers with 1 mbyte. in fixed buffer mode, each port is assigned a fixed number of receive buffers. there are 320 buffers available per port with 2 mbyte of dram, 140 buffers with 1 mbyte. the overflow of the rx buffer threshold is indicated by the receive buffer full led in the serial led interfaces. this indication is active only in fixed buffer mode. read pointer write pointer 21 byte count blk addr 10 9 0 frame #0 frame #1 frame #2 receive buffer (for all ports and pci) tx descriptors: 1024 x 3 rx empty list dram gt-48006 m/u 20 frame #n
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 13 8. packet forwarding the following sections describe the procedures for forwarding packets in the following situations: ? a unicast packet ? a multicast packet 8.1 forwarding a unicast packet across the bridge the sequence for forwarding a unicast packet across the bridge is as follows: 1. the incoming packet is fed to the rx fifo (there is an 20x32-bit rx fifo per port) and is transferred to an empty block in the receive buffer area of dram. 2. in parallel, an address recognition cycle is performed for both the da and the sa. the GT-48006A uses the das corresponding port number to queue the packet to the other port, or to drop the packet if the destination port equals the source port. 3. at the end of an error-free packet transfer, packet information is written to the output ports transmit descriptor. this information includes the byte count and the receive buffer block address which is pointed to by the write pointer. 4. the write pointer of the outgoing ports transmit descriptor is incremented. the target device transmits whenever the write pointer is not equal to the read pointer. 5. at the end of the packet transmit process, the target device increments the read pointer and clears the appropri- ate bit in the empty list. 8.2 forwarding a multicast packet the GT-48006A forwards multicast packets across the bridge using the same mechanism as described for unicast packets. multicast and broadcast packets are not re-sent on the input port. 8.3 tx watchdog timer the GT-48006A includes a transmit watchdog timer for each transmit queue. for 100mbps operation, the value of the timer is 63msec. for 10mbps operation, the default value of the timer is 630msec. the timer measures the time between the transmission of two consecutive outgoing packets. when the timer expires, the GT-48006A clears the appropriate used blocks.
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 14 9. fast ethernet interfaces the GT-48006A interfaces directly to two mii (media independent interface) ports which are compliant with the ieee standard (please see 802.3u fast ethernet standard for detailed interface information and timing parameters). each mii port has the following characteristics: ? capable of supporting both 10 mbps and 100 mbps data rates in half or full duplex modes ? data and delimiters are synchronous to clock references ? provides independent 4-bit wide transmit and receive paths ? uses ttl signal levels ? provides a simple management interface (common to all ports) ? capable of driving a limited length of shielded cable the GT-48006A incorporates all the required digital circuitry to interface to 100basetx, 100baset4, and 100basefx. 9.1 10/100 mii compatible interface the GT-48006A mac allows it to be connected to a 10mbps or 100mbps network. the GT-48006A interfaces to an ieee 802.3u 10/100 mbps mii compatible phy device. the data path consists of a separate nibble-wide stream for both transmit and receive data. the GT-48006A can switch automatically between 10 or 100 mbps operation depend- ing on the speed of the network. data transfers are clocked by the 25 mhz transmit and receive clocks in 100 mbps operation, or by 2.5 mhz transmit and receive clocks in 10 mbps operation. the clock inputs are driven by the phy, which controls the clock rate based on auto-negotiation. 9.2 media access control (mac) the GT-48006A mac performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, col- lision handling, deferral to link traffic, etc. the GT-48006A ensures that any outgoing packet complies with the 802.3 specification in terms of preamble structure. the GT-48006A transmits 56 preamble bits before start of frame delim- iter (sfd). the GT-48006A operates in half-duplex or full-duplex modes. in half-duplex mode, the GT-48006A checks that there is no competitor for the network bus before transmission. in addition to listening for a clear line before trans- mitting, the GT-48006A handles collisions in a pre-determined way. if two nodes attempt to transmit at the same time, the signals collide and the data on the line is garbled. the GT-48006A listens while it is transmitting, and it can detect a collision. if a collision is detected, the GT-48006A transmits a jam pattern and then delays its re-transmission for a random time period determined by the backoff algorithm. in full-duplex mode, the GT-48006A transmits unconditionally. 9.3 auto-negotiation 9.3.1 disabled autonegotiation can be disabled for a port through the state of the daddr[1:0] pins at reset. following reset the port duplex mode is set by the state sampled on daddr[6] for port 0 and daddr[7] for port 1. the speed that each port oper- ates in (10mbps or 100mbps) is determined by the frequency of txclk[x] and rxclk[x] generated by the phy. when the port is operating at 10mbps, the phy generates a 2.5mhz clock for both txclk and rxclk. when the port is operating at 100mbps, the phy generates a 25mhz clock for both txclk and rxclk. 9.3.2 enabled when auto-negotiation is enabled for a port the GT-48006A decodes the duplex mode for each port from the values of the auto-negotiation advertisement register and the auto-negotiation link partner ability registers at the end of the auto-negotiation process. note: if autonegotiation is enabled for either port, then the link status for both ports will be determined auto- matically by the GT-48006A by reading the phy status registers. force link pass overrides the phy in this mode. the auto-negotiation feature on the GT-48006A is used only to tell the GT-48006A the duplex status of each port. the speed (10/100) of each port is determined only by rxclk and txclk. the GT-48006A will continuously perform the fol- lowing operations for each port (phy addresses 1 and 2 alternately), implemented as read commands issued via the
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 15 mdc/mdio interface: 1. read the phy auto-negotiation complete status. as long as phy bit 1.5 (register 1, bit 5) is '0' switch to half- duplex mode and continue to read phy register bit 1.5. continue to step 2 when phy bit 1.5 is '1', signaling auto- negotiation is complete. steps 2 through 6 are performed once for every transition of phy bit 1.5 from '0' to '1'. once phy bit 1.5 remains '1' and phy registers 4 and 5 have already been read, the GT-48006A will continue to read phy register 1, and monitor phy bit 1.5. steps 2 to 6 are performed once, if after rst* de-assertion, the phy bit 1.5 is read as '1', in order to update the GT-48006A duplex mode. note: phy bit 1.2 (link status) is read and latched during this same register read operation, regardless of the auto- negotiation status. 2. read the auto-negotiation advertisement register, phy register 4. continue to step 3. 3. read the auto-negotiation link partner ability register, phy register 5. continue to step 4. 4. resolve the highest common ability of the two link partners in the following manner (according to the 802.3u prior- ity resolution clause 28b.3): if (bit 4.8 and bit 5.8) == '1' then ability is 100base-tx full duplex else if (bit 4.9 and bit 5.9) == '1' then ability is 100base-t4 half duplex else if (bit 4.7 and bit 5.7) == '1' then ability is 100base-tx half duplex else if (bit 4.6 and bit 5.6) == '1' then ability is 10base-t full duplex else ability is 10base-t half duplex; continue to step 5. 5. resolve the duplex mode of the two link partners in the following manner: if ( (ability == "100base-tx full duplex") or (ability == "10base-t full duplex") ) then duplex mode = full duplex else duplex mode = half duplex; note: the value of the duplex mode indication should change only after reading both phy registers 4 and 5. continue to step 6. 6. update the GT-48006A mac. continue with step 1. 9.4 backoff algorithm options the GT-48006A implements the truncated exponential backoff algorithm defined by the 802.3 standard. aggressive- ness of the backoff algorithm used by all of the ports is controlled by the limit4 pin. limit4 controls the number of con- secutive packet collisions that will occur before the consecutive collision counter is reset. when limit4 is low, the gt- 48006a resets the collision counter after 16 consecutive retransmit trials, restarts the backoff algorithm, and continues to try and retransmit the frame. a packet which is endlessly colliding on re-transmits will continue to be re-transmitted forever, only changing backoff intervals. the retransmission is done from the data already stored in the dram. in the case of a successful transmission, the GT-48006A is ready to transmit any other frames queued in its transmit fifo within the minimum ipg of the link. when limit4 is high, the GT-48006A will reset its collision counter and restarts the backoff algorithm after 4 consecu- tive transmit trials. this results in the GT-48006A being more aggressive in acquiring the media following a collision. this will result in better overall switch throughput (less packet loss) in standardized tests. limit4 can be toggled during switch operation.
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 16 9.5 data blinder the internal data blinder field sets the period of time during which the port does not look at the wire to decide to trans- mit (inhibit time.) the value is fixed at 32 bit times. 9.6 inter-packet gap (ipg) ipg is the idle time between any two successive packets from the same port. the value (from the standard) is 9.6us for 10mbps ethernet and 960nsec for 100-mbps fast ethernet. 9.7 10/100 mbps mii transmission (half-duplex) when the GT-48006A has a frame ready for transmission, it samples the link activity. if the rxdv signal is inactive (no activity on the link), and the inter-packet gap (ipg) counter has expired, frame transmission begins. the data is trans- mitted via pins txd[3:0] of the transmitting port, clocked on the rising edge of txclk. the signal txen is asserted at this same time. in the case of collision, the phy asserts the col signal on the GT-48006A which will then stop transmitting the frame and transmit a jam sequence onto the link. after the end of a collided transmission, the GT-48006A will back off and attempt to retransmit once the backoff counter expires. a waveform of the signals which are synchronous to txclk (txd0[3:0], txd1[3:0], txen[1:0]) is shown in figure 2. the actual delay times of the GT-48006A are tighter than the ieee 802.3u standard, clause 22.3.1, as shown in table 3. figure 2: mii transmit signal timing table 3: mii signal timings synchronous to txclk 9.8 10/100 mbps mii reception (half-duplex) frame reception starts with the assertion of rxdv (while the GT-48006A is not transmitting) by the phy. once rxdv is asserted, the GT-48006A will begin sampling incoming data on pins rxdv[3:0] on the rising edge of rxclk. reception ends when the rxdv is deasserted by the phy. the last nibble sampled by the GT-48006A is the nibble present on rxd[3:0] on the last rxclk rising edge in which rxdv is still asserted. during reception, the rxdv is asserted. if, while rxdv is asserted, the GT-48006A detects the assertion of rxer, it will designate this packet as corrupted. while no reception is taking place, rxdv should remain deasserted. a waveform of the signals which are synchronous to rxclk (rxd0[3:0], rxd1[3:0], rxdv[1:0], rxer[1:0]) is shown in figure 3. the setup and hold times of the GT-48006A are tighter than the ieee 802.3u standard, clause 22.3.2, as shown in table 4. GT-48006A ieee 802.3u spec. name parameter min max min max units vd valid delay after rising txclk 2 14 0 25 ns vd txclk txd, txen vih min vil max vih min vil max
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 17 figure 3: mii receive signal timing table 4: mii signal timings synchronous to rxclk 9.9 10/100 mbps full-duplex operation when operating in full-duplex mode the GT-48006A can transmit and receive frames simultaneously. in full-duplex mode, the crs signal is associated with received frames only and has no effect on transmitted frames. the col signal is ignored by the GT-48006A while in full-duplex mode. transmission starts when txen goes active. transmission starts regardless of the state of rxdv. reception starts when the rxdv signal is asserted indicating traffic on the receive port of the phy. 9.10 illegal frames the GT-48006A will discard all illegal frames. examples include: runts (less than 64 bytes), oversize (greater than 1518 or 1522 bytes), and bad fcs (bad crc.) 9.11 backpressure backpressure is supported for half-duplex operation. when the GT-48006A cannot allocate a receive buffer for an incoming packet, the device will transmit a jamming pattern on the port, thus forcing a collision. backpressure is not active in full-duplex mode. backpressure is enabled via a reset strapping option as shown in table 1 on page 7. backpressure is not active when dynamic buffer mode is enabled (see section 7.1). 9.12 vlan tagging support the GT-48006A will pass 802.1q frames (i.e. frames up to 1522 bytes) if the vl tag enable is selected at reset via the dadr[4] pin. GT-48006A ieee 802.3u spec. name parameter min max min max units ts setup time to rising rxclk 6 10 ns th hold time after rising rxclk 1 10 ns ts rxclk rxd, rxdv, rxer th vih min vil max vih min vil max
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 18 10. mii management interface (smi) the GT-48006A mac contains an mii management interface (smi) for an mii compliant phy devices. this allows con- trol and status parameters to be passed between the GT-48006A and the phy by one serial pin (mdio) and a clocking pin (mdc), reducing the number of control pins required for phy mode control. typically, the GT-48006A will continu- ously query the phy devices for their link status. the predefined phy addresses for the link query are 1 and 2 (out of possible 32 addresses). 10.1 smi cycles the smi protocol consists of a bit stream that is driven or sampled by the GT-48006A on each rising edge of the mdc clock. the bit stream format of the smi frame is described in table 5. ? pre (preamble). at the beginning of each transaction, the GT-48006A sends a sequence of 32 contiguous logic one bits on mdio with 32 corresponding cycles on mdc to provide the phy with a pattern that it can use to establish synchronization. ? st (start of frame). a start of frame pattern of 01. ? op (operation code). 10 - read; 01 - write ? phyad (phy address). a 5 bit address of the phy device (32 possible addresses). the first phy address bit transmitted by the GT-48006A is the msb of the address. ? regad (register address). a 5 bit address of the phy register (32 possible registers in each phy). the first register address bit transmitted by the GT-48006A is the msb of the address. the GT-48006A always queries the phy device for status of the link by reading register 1, bit 2. ? ta (turn around). the turnaround time is a 2 bit time spacing between the register address field and the data field of the smi frame to avoid contention during a read transaction. during a read transaction the phy should not drive mdio in the first bit time and drive 0 in the second bit time. during a write transaction, the gt- 48006a drives a 10 pattern to fill the ta time. ? data (data). the data field is 16 bits long. the phy drives the data field during read transactions. the gt- 48006a drives the data field during write transactions. the first data bit transmitted and received shall be bit 15 of the phy register being addressed. ? idle (idle). the idle condition on mdio is a high impedance state. the mdio driver is disabled and the phy should pull-up the mdio line to a logic one. 10.1.1 smi timing requirements figure 4 shows a waveform of the mdc line which is driven by the GT-48006A. table 6 shows typical mdc timings. figure 4: GT-48006A mdc waveform table 5: smi bit stream format pre st op phyad regad ta data idle read 1...1 01 10 aaaaa rrrrr z0 d..d(16) z write 1...1 01 01 aaaaa rrrrr 10 d..d(16) z t1 mdc vih min vil max t2 t3
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 19 table 6: typical mdc timings a waveform of the mdio line when it is driven by the GT-48006A is shown in figure 5. the actual delay times of the GT-48006A are tighter than the ieee 802.3u standard, clause 22.3.4, as shown in table 7. figure 5: GT-48006A mdio output delay table 7: mdio signal timings ( GT-48006A driving mdio) a waveform of the mdio line when it is driven by the phy is shown in figure 6. the setup and hold times requirements of the GT-48006A are the same as the ieee 802.3u standard, clause 22.3.4, as shown in table 8. figure 6: GT-48006A mdio setup and hold time 1. mdc is generated internally by dividing the clk clock input by 32. clk clock frequency of 33mhz is assumed. GT-48006A name parameter typical units t1 mdc high time 480 ns t2 mdc low time 480 ns t3 1 mdc period 960 ns GT-48006A ieee 802.3u spec. name parameter min max min max units t4 rising mdc to valid mdio 10 50 0 300 ns t4 mdc mdio vih min vil max vih min vil max t5 mdc mdio t6 vih min vil max vih min vil max
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 20 table 8: mdio signal timings (phy driving mdio) 10.2 link detection and link detection bypass (forcelinkpass*) typically, the GT-48006A will continuously query the phy devices for its link status. the predefined phy addresses for the link query are 1 and 2 (out of possible 32 addresses). the GT-48006A will alternately read register 1 from phy1 and phy2 and update the internal link bits according to the value of bit 2 of register 1. in the case of link is down (i.e. bit 2 is 0), that port will enter link test fail state. in this state, all of the ports logic is reset. the port will exit f rom link test fail state only when the link is up i.e. bit 2 of register 1 is read from the ports phy as 1. the GT-48006A offers the option to disable the link detection mechanism by forcing the link state of both ports to the link test pass state regardless of the phys link bit value. this is done with the ledstb pin, which is sampled at reset (see table 1 on page 7). GT-48006A ieee 802.3u spec. name parameter min max min max units t5 setup time to rising mdc 10 10 ns t6 hold time after rising mdc 10 10 ns
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 21 11. dram interface and usage the GT-48006A includes direct support for edo drams. the performance of edo satisfies the required bandwidth for wire-speed data transfer, address recognition and tx descriptor fetch/update. the dram interface is entirely glueless. all accesses are performed as 32-bits. the dram interface is designed for 50ns edo drams and all timings are guar- anteed to work with these devices. refresh is performed automatically by the GT-48006A. please refer to the ev- 48006 evaluation platform schematics for an example of edo dram design with the GT-48006A. the GT-48006A requires about 300kbytes of the dram for the address table and other private data structures. the remainder is used for packet buffers. following power-up or system reset, the GT-48006A device creates the mac address table in dram, and initializes all locations in the table to indicate that invalid entries exist in all locations. galileo recommends using dram with 256k x 16 configuration. when using this configuration, 2 dram chips are required for 1 mbyte, and 4 dram chips are required for 2 mbytes. if 1 mbyte is selected, ras0* should be connected to 2 dram chips while ras1* should be left unconnected. if 2 mbytes is selected, ras0* will control the first 1mb bank, while ras1* will activate the second 1mb bank. ddata[31:0], daddr[8:0], cas*, and we* should be connected to both banks. using 1 or 2 mbytes of dram is entirely up to the architect. 2mbytes increases the size of the rx buffer space. this performance advantage must be weighed against the cost of additional memory. 12. led support the GT-48006As serial led interface is similar to the 3-pin led interface of the gt-48001a device which requires a pal to interpret the led bit stream. galileo provides reference designs and example pal equations in the led inter- face application note available on our website. 12.1 led indications interface description table 9 on page 21 shows the data accessible on the led indications serial interface for both GT-48006A ports. 12.2 detailed led signal description 12.2.1 primary port status led the primary port status led provides the following information: if link integrity test failed port status led blinks once; else everything is ok (port status led is on) 12.2.1.1 status led blink timing link integrity test failed, status led blinks once. primary status bit is active for 500 ms every 5s. table 9: led signals available data description symbolic signal name type primary port status led primary_port_status n/a transmit data in progress transmit dynamic receive data in progress receive dynamic collision active collision dynamic full/half duplex full_duplex static receive buffer full rx_buffer_full dynamic
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 22 12.2.2 transmit data in progress this signal indicates the port is transmitting data. 12.2.3 receive data in progress this signal indicates port receive activity. 12.2.4 collision active this signal indicates the port collision event detected by the port. 12.2.5 full/half duplex this signal indicates the port duplex: active - full duplex, inactive - half duplex. 12.2.6 receive buffer full in order for this led to be active, rx buffer threshold must be enabled (i.e. the GT-48006A must be in fixed buffer allo- cation mode.) this signal indicates the port receive buffer status: active - the buffer exceeds it's programmed threshold, inactive otherwise. 12.2.7 link fail state this signal indicates the port link status: active - link is down, inactive - link is up. 12.2.8 pure port status led this signal will be inactive for the following event: ? link integrity test failed otherwise, this signal is active. 12.3 led signals timing type 12.3.1 static led signals these signals are stable for relatively long time periods. the led indication directly reflects their current value. the stat- ic signals are: 500ms 5 seconds link integrity test fails: primary status led blinks 500ms every 5 seconds
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 23 ? port status ? forwarding of unknown packets enabled ? full/half duplex 12.3.2 dynamic internal signals: these signals are typically active for short time periods. in order to be visible through the led indication interfaces, the GT-48006A includes a "monostable" function per each of these dynamic signals so they can be viewed on the led in- dication output for a period of about 62 ms. the dynamic signals are: ? port status ? transmit data in progress (txen) ? receive data in progress (rxdv) ? collision active (col) ? receive buffer full 12.4 serial led interface description the led serial interface consists of three outputs: ? ledclk : ledclk is the primary timebase of the led indications interface. it is a 50% duty cycle free running clock at a fixed frequency of 1 mhz. ledclk is high-z when rst* is asserted. ? ledstb : ledstb (active high) indicates the beginning of the data frame. ledstb is activated for a duration of one ledclk cycle once every 128 ledclk cycles, starting from rst* deactivation. this signal marks the begin- ning of the 128 bit long led data frame. ledstb transitions occur 90 ns after ledclk rising edge. ? leddata : the internal signals are multiplexed on the leddata output for every data frame. ledstb activation signals the presence of data bit #1 (out of 128 bits) on the leddata output. leddata transitions occur 90 ns after ledclk rising edge. all internal signals accessible via leddata are active high internally and are inverted on the leddata output (i.e. when an internal signal is active, the data bit on the leddata output will be low). for example: if port 0 transmits data, the internal_event_transmit[0] signal is active high and the corresponding bit 9 in the leddata serial stream is low. the timings for the led serial interface are shown in figure 7. figure 7: serial led interface timings 12.4.1 table of internal activities/status driven via the serial led interface the following table defines a bit by bit description of the internal signals driven through the led indications serial inter- face. the bit number refers to the activation of ledstb. ledstb is active for bit# 1. reserved bit contents are not defined (i.e. can be either high or low). ledclk 1us 90ns 90ns ledstb leddata
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 24 table 10: led signals bit number signal bit number signal 1 primary_port_status[0] 22 -reserved- 2 primary_port_status[1] 23 full_duplex[1] 3-8 -reserved- 24-72 -reserved- 9 transmit[0] 73 link_test_fail[0] 10 receive[0] 74 link_test_fail[1] 11 collision[0] 75-97 -reserved- 12 rx_buffer_full[0] 97 pure_port_status[0] 13 -reserved- 98 pure_port_status[1] 14 -reserved- 99-128 -reserved- 15 full_duplex[0] 16 -reserved- 17 transmit[1] 18 receive[1] 19 collision[1] 20 rx_buffer_full[1] 21 -reserved-
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 25 13. pinout for 100 pin pqfp pin # signal name pin # signal name pin # signal name 1 ddata[31] 36 ddata[2] 71 gnd 2 ddata[30] 37 gnd 72 col[0] 3 ddata[29] 38 ddata[1] 73 txen[1] 4 gnd 39 ddata[0] 74 txclk[1] 5 ddata[28] 40 cas* 75 vtol 6 ddata[27] 41 we* 76 txd1[3] 7 ddata[26] 42 vdd 77 vdd 8 ddata[25] 43 ras[1]* 78 txd1[2] 9 ddata[24] 44 ras[0]* 79 txd1[1] 10 vdd 45 daddr[8] 80 txd1[0] 11 ddata[23] 46 daddr[7] 81 rxd1[3] 12 ddata[22] 47 daddr[6] 82 rxd1[2] 13 ddata[21] 48 daddr[5] 83 rxd1[1] 14 ddata[20] 49 daddr[4] 84 vdd 15 ddata[19] 50 daddr[3] 85 rxd1[0] 16 ddata[18] 51 daddr[2] 86 rxer[1] 17 ddata[17] 52 daddr[1] 87 rxclk[1] 18 ddata[16] 53 daddr[0] 88 gnd 19 ddata[15] 54 gnd 89 rxdv[1] 20 gnd 55 txen[0] 90 crs[1] 21 ddata[14] 56 txclk[0] 91 col[1] 22 ddata[13] 57 txd0[3] 92 mdc 23 ddata[12] 58 txd0[2] 93 mdio 24 ddata[11] 59 txd0[1] 94 scan* 25 vtol (future: aging) 60 txd0[0] 95 gnd 26 ddata[10] 61 clk 96 tristate* 27 ddata[9] 62 rxd0[3] 97 ledclk 28 ddata[8] 63 gnd 98 leddata 29 gnd 64 rxd0[2] 99 ledstb 30 ddata[7] 65 rxd0[1] 100 rst* 31 ddata[6] 66 rxd0[0] 32 ddata[5] 67 rxer[0] 33 vdd 68 rxclk[0] 34 ddata[4] 69 rxdv[0]
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 26 35 ddata[3] 70 crs[0] note: vtol pins were shown as vdd in the last version o f this document and in recent pinout lists . pin 25 is currently used as a vtol pin, and must be tied high for proper operation. in a future revi- sion, automatic address aging will be supported, and this pin will control this operation. see section 6.3 for more information. pin # signal name pin # signal name pin # signal name
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 27 14. dc characteristics - preliminary/subject to change 14.1 absolute maximum ratings 14.2 recommended operating conditions 14.3 dc electrical characteristics over operating range (tc=0-80 c; vdd=+3.3v, +/-5%) 1. this voltage does not apply to clk. clk is not 5v tolerant. 1. this voltage does not apply to clk. clk is not 5v tolerant. symbol parameter min. max. unit vdd supply voltage -0.3 3.6 v vtol input voltage tolerance protection pins 1 3.0 5.25 v vi input voltage -0.3 vtol+0.3 v vo output voltage -0.3 vdd+0.3 v io output current 24 ma iik input protect diode current ma iok output protect diode current ma tc operating case temperature 0 70 c tstg storage temperature -40 125 c symbol parameter min. typ. max. unit vdd supply voltage 3.0 3.6 v vtol i/o voltage tolerance protection voltage (3.3v i/o) 3.0 3.6 v vtol i/o voltage tolerance protection voltage (5.0v i/o) 1 4.75 5.25 v vi input voltage 0 vdd v vo output voltage 0 vdd v tc case operating temperature 0 70 c cin input capacitance pf cout output capacitance pf symbol parameter test condition min. typ. max. unit vih input high level guaranteed logic high level 2.0 v vil input low level guaranteed logic low level 0.8 v voh output high voltage ioh = 2 ma ioh = 4 ma ioh = 8 ma ioh = 12 ma ioh = 16 ma ioh = 24 ma 2.4 vdd v
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 28 note: pullup/pulldown resistors are 45kohm minimum, 65kohm typical, 80kohm maximum. 14.4 thermal data vol output low voltage iol = 2 ma iol = 4 ma iol = 8 ma iol = 12 ma iol = 16 ma iol = 24 ma 00.4v iih input high current +-1 ua iil input low current +-1 ua iozh high impedance output current +-1 ua iozl high impedance output current +-1 ua icc operating current vdd = 3.45v f=40mhz 175 ma table 11: 100 pqfp thermal data parameter definition value q ja thermal resistance: junction to ambient, 0 ft./s airflow 42.0 c/w symbol parameter test condition min. typ. max. unit
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 29 15. ac timing - preliminary/subject to change (tc= 0-70 o c; vdd= +3.3v, +/- 5%) notes: 1. all delays, setup, and hold times are referred to clk rising edge, unless stated otherwise. 2. all outputs are specified for 50pf load. 3. all inputs and all outputs also refer to i/o signal behavior. figure 8: output delay from rising edge symbol signals description min max unit clk system clock 30 40 mhz clk rise/fall time 1 4 v/ns rst* t3 daddr[8:0], ddata[31:0], cas*, ras*, we* delay from clock rising or falling edge 2 13 ns t4 ddata[31:0] setup 10 ns t5 ddata[31:0] hold 1 ns t6 ddata[31:0] float delay 2 16 ns t7 ddata[31:0] drive delay 2 10 ns t3 min clk output t3 max
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 30 figure 9: input setup and hold figure 10: output delay from clock figure 11: output float and drive delay valid t4 t5 clk input t3 min t3 max clk output clk valid valid output t6 t7
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 31 16. functional waveforms figure 12: edo dram read figure 13: edo dram write rc0c1c2c3 d0 d3 d2 d1 clk daddr[8:0] ras* cas* we* ddata[31:0] data sampled at arrow tip rc0 c3 c2 c1 d3 d2 d1 d0 clk daddr[8:0] ras* cas* we* ddata[31:0]
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 32 17. packaging figure 14: 100 lead pqfp package outline
GT-48006A low cost two port 10/100 ethernet bridge/switch controller 33 18. document history table 12: document history document type rev. number date comments preliminary rev 1.1 6/17/98 added definition for pin 25, aging. increase temperature specification. removed thermal resistance: junction to case. preliminary 1.2 8/3/98 set minimum clk frequency restriction (min.=30mhz, max.=40mhz).

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